KEY CONTENTS OF THIS WORKSHOP
• Introduction to Xilinx 7 series FPGA , Vivado and ZynQ 7000 SoC
• Creating an HDL Design, Synthesis and Implementation with Xilinx Vivado
• Hardware Debugging, Monitoring and driving of real time FPGA signals
• Extending the hardware design by adding AXI peripheral using IP catalog
• Creating and adding own custom Peripheral IP
• Interfacing Peripheral Modules with Zynq
• Invoking PLL module for clock generation
• Interfacing WiFi module using Zynq
7000 series Zedboard
• Creating an HTML page and Visualizing the
data in the webserver.
DESIGN CASE STUDY
A common case study will be provided for all the participants. The participants may work on the case study from their respective institutions and submit it within the stipulated time. Certificate of appreciation will be provided upon completion of the case study.